Data processing devices that include multiple processing engines, or cores, are known in the art. Typically, each respective core will have an associated working memory or cache. The availability of such working memory enables a processing engine of the processing device to temporarily access and store data for calculations and other work in progress in an efficient manner. Generally, this avoids having to await retrieval of data during the particular processing operation from a main memory or other source and also avoids having to store intermediate results of a particular processing operation to main memory.
Typically, a cache is configured to store a plurality of cache entries where each cache entry includes a cache line for data and a corresponding cache tag for address information associated with data stored in the cache line. Conventionally, the cache tag address information includes an invalidation flag with respect to each address stored in the cache tag. Where caches of different processors share information, invalidation flags can be used to assist in facilitating cache coherence policies, i.e. assuring that information shared by caches is the same or “valid” in each cache.
When data is accessed in a cache by its respective processing engine, it may be modified during a processing operation such that it may no longer reflect the contents of the main memory or other source where it had been retrieved. Conventionally, this results in the cache containing both “clean” and “dirty” data entries where a clean data entry accurately reflects the contents of main memory or other source as originally retrieved and where a dirty data entry may not. Caches may be configured to implement a “write through” policy such that anytime data is written back to the cache it is immediately written back to main memory which eliminates the dirty data issue. However, in various contexts, implementation of such “write through” policies may negatively effect performance or have other undesirable consequences.
With respect to cache coherency policies, there are various situations where there is an update to the value of a memory location causing a stored cache value to become invalid. Such situations and others can result in the generation of invalidation commands from various components of a data processing system.
For example, if a particular data entry in a cache is modified to contain dirty data, not only does it no longer match the data saved at the respective address in main memory, it also does not match the data for the respective address saved in other caches. Accordingly, in connection with writing dirty data to a cache, invalidation commands will be sent to other caches that are to be maintained as coherent to set to “invalid” the invalidation flag with respect to that same data address if it is stored in the other caches.
In any event, when a cache receives an invalidation command, it will normally process it to flag the corresponding data as invalid if data for the respective address if currently stored in the cache. At the same time, the cache may be receiving multiple other commands so that the order of processing commands requires arbitration and can produce processing delays, i.e. latency, in the processing of commands that can affect overall processing performance.
Caches coherence policies may generally be employed with any type or combination of types of data processing components, including, but not limited to, central processing units (CPUs), graphics processing units (GPUs), and accelerated processing units (APUs).